Maxim Integrated MAX2871ETJ+, PLL Clock Driver, 32-Pin TQFN

Output Binary Buffers/Dividers Enable Extended Frequency Range
Divider Ratios of 1/2/4/8/16/32/64/128
23.5MHz to 6000MHz
High-Performance Phase Frequency Detector (PFD) and Reference Frequency Reduces Spectral Noise
PFD Up to 140MHz
Reference Frequency Up to 210MHz
Low Normalized Inband Phase Noise of -230dBc/Hz Reduces System Noise Floor Contribution
Manual or Automatic VCO Selection Permits Fast Switching
Output Phase Reset and Adjustment Allow Synchronization of Multiple Synthesizers
On-Chip Temperature Sensor with 7-Bit ADC Ensures Optimum VCO Selection
Cycle Slip Reduction and Fast Lock Features Improve Accuracy and Acquisition Time
VCO Lock Maintained Over Entire Temperature Range Provides Glitch-Free Operation
Dual Differential Programmable Outputs Maximize Flexibility of Use
Applications
Clock Generation
Microwave Radios
Test and Measurement
Wireless Infrastructure

Datasheet -MAX2871ETJ+