* УТОЧНЯЙТЕ ВОЗМОЖНОСТЬ, ЦЕНУ И СРОК ПОСТАВКИ, В СВЯЗИ С ОГРАНИЧЕНИЕМ ЭКСПОРТА ТОВАРОВ ИЗ СТРАН ЕС И ВЕЛИКОБРИТАНИИ
The Renesas Electronics IDT8SLVD1204-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204-33I ideal for those clock distribution applications demanding well-defined performance and repeatability.
Four low skew, low additive jitter LVDS output pairs Two selectable differential clock input pairsDifferential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECLMaximum input clock frequency: 2GHzLVCMOS/LVTTL interface levels for the control input select pinOutput skew: 20ps (maximum)Propagation delay: 310ps (maximum)Low additive phase jitter, RMS","fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 100fs (maximum)
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