9DB106BGILF Number of Drivers, Renesas Electronics 9DB106BGILF, LVDS Buffer 6 TTL Buffer, 20-Pin TSSOP

The Renesas Electronics 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.
6 - 0.7 V current mode differential output pairs (HCSL)CLKREQ# pin for outputs 1 and 4/ supports Express Card applicationsPLL or bypass mode/PLL can dejitter incoming clockSelectable PLL bandwidth/minimizes jitter peaking in downstream PLL'sSpread Spectrum Compatible/tracks spreading input clock for low EMISMBus Interface/unused outputs can be disabledCycle-to-cycle jitter 50 psOutput-to-output skew 50 ps