74LVC125APW,112 Logic Function, Nexperia 74LVC125APW,112 Buffer, Line Driver Logic Gate, 14-Pin TSSOP

74LVC Family Inverters \u0026 Buffers
Low-Voltage CMOS logicSingle gate packageOperating Voltage: 1.65 to 5.5 VCompatibility: Input LVTTL/TTL, Output LVCMOS
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs.
Mixed 5 V and 3.3 V applicationsImproved current drive and voltage level of signalsImproved signal integrity for complex layoutsWide supply voltage rangeLow propagation delayTTL input options3-state output optionsOvervoltage tolerant optionsRegistered optionsKey applicationsLCD TVCell phonesIndustrial monitoringSTB
74LVC Family