* УТОЧНЯЙТЕ ВОЗМОЖНОСТЬ, ЦЕНУ И СРОК ПОСТАВКИ, В СВЯЗИ С ОГРАНИЧЕНИЕМ ЭКСПОРТА ТОВАРОВ ИЗ СТРАН ЕС И ВЕЛИКОБРИТАНИИ
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Mixed 5 V and 3.3 V applicationsImproved signal integrity with integrated termination resistorsHigh noise immunityFlow through pin out for easy layoutWide supply voltage rangeLow propagation delayOvervoltage tolerant input optionsIntegrated source termination resistor optionsBus hold optionsFrequency divisionControlled delaysInterface between asynchronous and synchronous systems
ESD Control Selection Guide V1
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