S27KS0641DPBHI020 Memory Size, Cypress Semiconductor S27KS0641DPBHI020, SDRAM 64Mbit Surface Mount, 333Mbit/s, 24-Pin FBGA

3.0 V I/O, 11 bus signalsSingle ended clock (CK)1.8 V I/O, 12 bus signalsDifferential clock (CK, CK#)Chip Select (CS#)8-bit data bus (DQ[7:0])Read-Write Data Strobe (RWDS)Bidirectional Data Strobe / MaskOutput at the start of all transactions to indicate refresh latencyOutput during read transactions as Read Data StrobeInput during write transactions as Write Data MaskRWDS DCARS TimingDuring read transactions RWDS is offset by a second clock, phase shifted from CKThe Phase Shifted Clock is used to move the RWDS transition edge within the read data eyeUp to 333 MBpsDouble-Data Rate (DDR) - two data transfers per clock166 MHz clock rate (333 MBps) at 1.8 V VCC100 MHz clock rate (200 MBps) at 3.0 V VCCSequential burst transactionsConfigurable Burst CharacteristicsWrapped burst lengths: 16 bytes (8 clocks)32 bytes (16 clocks)64 bytes (32 clocks)128 bytes (64 clocks)Linear burstHybrid option - one wrapped burst followed by linear burstWrapped or linear burst type selected in each transactionConfigurable output drive strengthLow Power ModesDeep Power DownPackage 24-ball FBGA