W9712G6KB25I Memory Size, Winbond W9712G6KB25I, SDRAM 128Mbit Surface Mount, 84-Pin TFBGA

The W9712G6KB is a 128M bits DDR2 SDRAM and speed involving -25, 25I and -3.
Double Data Rate architecture: two data transfers per clock cycleCAS Latency: 3, 4, 5 and 6Burst Length: 4 and 8Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with dataEdge-aligned with Read data and center-aligned with Write dataDLL aligns DQ and DQS transitions with clockDifferential clock inputs (CLK and /CLK)Data masks (DM) for write dataCommands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQSPosted /CAS programmable additive latency supported to make command and data bus efficiencyRead Latency = Additive Latency plus CAS Latency (RL = AL + CL)Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal qualityAuto-precharge operation for read and write burstsAuto Refresh and Self Refresh modesPrecharged Power Down and Active Power DownWrite Data MaskWrite Latency = Read Latency - 1 (WL = RL - 1)Interface: SSTL_18