* УТОЧНЯЙТЕ ВОЗМОЖНОСТЬ, ЦЕНУ И СРОК ПОСТАВКИ, В СВЯЗИ С ОГРАНИЧЕНИЕМ ЭКСПОРТА ТОВАРОВ ИЗ СТРАН ЕС И ВЕЛИКОБРИТАНИИ
Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
Fit-, form-, and function-compatible with the FX2
Pin-compatible 0
Object-code-compatible
Functionally compatible (FX2LP is a superset)
Ideal for bus- and battery-powered applications
Internal RAM, which is downloaded through USB
Internal RAM, which is loaded from EEPROM
Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints
Buffering options: Double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64-byte endpoint
Smart media standard ECC generation
GPIF™ (general programmable interface)
Enables direct connection to most parallel interfaces
Programmable waveform descriptors and configuration
registers to define waveforms
Integrated, industry-standard, enhanced 8051
Expanded interrupt system
Vectored USB interrupts and GPIF/FIFO interrupts
Separate data buffers for the setup and data portions of a
CONTROL transfer
Automatic conversion to and from 16-bit buses
Master or slave operation
Uses external clock or asynchronous strobes
Easy interface to ASIC and DSP ICs
Datasheet CY7C68014A-128AXC
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