CY7C1412KV18-250BZXC Memory Size, CY7C1412KV18-250BZXC | Cypress Semiconductor, CY7C1412KV18-250B

The Cypress Semiconductor CY7C1412KV18 series are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
333 MHz clock for high bandwidthTwo-word burst on all accessesDouble data rate (DDR) Interfaces on both read and write ports at 333 MHzTwo input clocks for precise DDR timingTwo input clocks for output data to minimize clock skew and flight time mismatchesEcho clocks simplify data capture in high speed systemsSingle multiplexed address input bus latches address inputs for both read and write ports