85104AGILF Logic Function, Renesas Electronics 85104AGILF, Clock Buffer, 5-Input, 20-Pin TSSOP

The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Four 0.7V differential HCSL outputsSelectable differential CLK0, nCLK0 or LVCMOS inputsCLK0, nCLK0 pair can accept the following differentialinput levels: LVPECL, LVDS, LVHSTL, HCSLCLK1 can accept the following input levels:LVCMOS or LVTTLMaximum output frequency: 500MHzTranslates any single-ended input signal to 3.3VHCSL levels with resistor bias on nCLK inputOutput skew: 100ps (maximum)Part-to-part skew: 600ps (maximum)Propagation delay: 3.2ns (maximum)Additive phase jitter, RMS: 0.22ps (typical)