Renesas Electronics 9DB1233AGLF Clock Buffer 64-Pin TSSOP-64

The Renesas Electronics 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.

3 selectable SMBus addresses
multiple devices can share the
same SMBus segment
12 OE# pins
hardware control of each output
PLL or bypass mode
PLL can dejitter incoming clock
Selectable PLL bandwidth
minimizes jitter peaking in
downstream PLLs
Spread spectrum compatible
tracks spreading input clock for
low EMI
SMBus interface
unused outputs can be disabled
Undriven differential outputs in Power-down
improved power
management

Datasheet - 9DB1233AGLF