Renesas Electronics 9DB102BGLF Clock Buffer 20-Pin TSSOP

The Renesas Electronics zero-delay buffer supports PCI express clocking requirements. it is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL band width to maximize performance in systems with or without spread-spectrum clocking.

CLKREQ pin for outputs 1 and 4/output enable for express card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
Spread spectrum compatible/tracks spreading input clock for low EMI
SMBus interface/unused outputs can be disabled
Industrial temperature range available

Datasheet - 9DB102BGLF